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cy7c1041bnv33 256 k 16 static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-06434 rev. *f revised april 9, 2014 256 k 16 static ram features high speed ? t aa = 12 ns low active power ? 612 mw (max.) low cmos standby power ? 1.8 mw (max.) 2.0 v data retention (660 ? w at 2.0 v retention) automatic power-down when deselected ttl-compatible inputs and outputs easy memory expansion with ce and oe features functional description the cy7c1041bnv33 is a high-performance cmos static ram organized as 262,144 words by 16 bits. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1041bnv33 is available in a standard 44-pin 400-mil-wide body width soj and 44-pin tsop ii package with center power and ground (revolutionary) pinout. 14 15 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 256k x 16 array a 0 a 11 a 13 a 12 a a a 16 a 17 a 9 a 10 1024 x 4096 i/o 0 ? i/o 7 oe i/o 8 ? i/o 15 ce we ble bhe logic block diagram
cy7c1041bnv33 document number: 001-06434 rev. *f page 2 of 14 contents pin configuration ............................................................. 3 selection guide ................................................................ 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 5 data retention waveform ................................................ 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 10 ordering code definitions ......................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 12 document conventions ................................................. 12 units of measure ....................................................... 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc? solutions ...................................................... 14 cypress developer community ................................. 14 technical support ................. .................................... 14
cy7c1041bnv33 document number: 001-06434 rev. *f page 3 of 14 pin configuration figure 1. 44-pin soj / tsop ii pinout (top view) top view soj tsop ii we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 3 a 4 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 16 a 15 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 14 a 13 a 12 a 11 a 9 a 10 nc selection guide description -12 maximum access time (ns) 12 maximum operating current (ma) commercial 190 maximum cmos standby current (ma) commercial 0.5
cy7c1041bnv33 document number: 001-06434 rev. *f page 4 of 14 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied ........... ............... ............... ?55 c to +125 c supply voltage on v cc to relative gnd [1] ...............................?0.5 v to +4.6 v dc voltage applied to outputs in high z state [1] ................................ ?0.5 v to v cc + 0.5 v dc input voltage [1] ............................ ?0.5 v to v cc + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage (mil-std-883, method 3015) ................................. > 2001 v latch up current ..................................................... > 200 ma operating range range ambient temperature [2] v cc commercial 0 c to +70 c 3.3 v 0.3 v electrical characteristics over the operating range parameter description test conditions -12 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage [1] ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc commercial ? 190 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?40ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3 v or v in < 0.3v, f = 0 commercial ? 0.5 ma notes 1. v il (min.) = ?2.0 v for pulse durations of less than 20 ns. 2. t a is the ?instant on? case temperature.
cy7c1041bnv33 document number: 001-06434 rev. *f page 5 of 14 capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v 8 pf c out i/o capacitance 8pf ac test loads and waveforms figure 2. ac test loads and waveforms data retention characteristics over the operating range parameter description conditions [4] min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ?330 ? a t cdr [3] chip deselect to data retention time 0?ns t r [5] operation recovery time t rc ?ns data retention waveform figure 3. data retention waveform 90% 10% 3.3 v gnd 90% 10% all input pulses 3.3 v output 30 pf including jig and scope output (a) (b) r1 317 ? 167 ? r2 351 ? venin equivalent th 1.73 v rise time: 1 v/ns fall time: 1 v/ns 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc notes 3. tested initially and after any design or proc ess changes that may affect these parameters. 4. no input may exceed v cc + 0.5 v. 5. t r < 3 ns for the -12 and -15 speeds.
cy7c1041bnv33 document number: 001-06434 rev. *f page 6 of 14 switching characteristics over the operating range parameter [6] description -12 unit min max read cycle t rc read cycle time 12 ? ns t aa address to data valid ? 12 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 12 ns t doe oe low to data valid ? 6 ns t lzoe oe low to low z 0 ? ns t hzoe oe high to high z [7, 8] ?6 ns t lzce ce low to low z [8] 3? ns t hzce ce high to high z [7, 8] ?6 ns t pu ce low to power-up 0 ? ns t pd ce high to power-down ? 12 ns t dbe byte enable to data valid ? 6 ns t lzbe byte enable to low z 0 ? ns t hzbe byte disable to high z ? 6 ns write cycle [9, 10] t wc write cycle time 12 ? ns t sce ce low to write end 10 ? ns t aw address set-up to write end 10 ? ns t ha address hold from write end 0 ? ns t sa address set-up to write start 0 ? ns t pwe we pulse width 10 ? ns t sd data set-up to write end 7 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [8] 3? ns t hzwe we low to high z [7, 8] ?6 ns t bw byte enable to end of write 10 ? ns notes 6. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 7. t hzoe , t hzce , and t hzwe are specified with a load capacit ance of 5 pf as in part (b) of figure 2 on page 5 . transition is measured 500 mv from steady-state voltage. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1041bnv33 document number: 001-06434 rev. *f page 7 of 14 switching waveforms figure 4. read cycle no. 1 [11, 12] figure 5. read cycle no. 2 (oe controlled) [12, 13] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce impedance address data out v cc supply t dbe t lzbe t hzce bhe ,ble current i sb i cc notes 11. device is continuously selected. oe , ce , bhe and/or bhe = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low.
cy7c1041bnv33 document number: 001-06434 rev. *f page 8 of 14 figure 6. write cycle no. 1 (ce controlled) [14, 15] figure 7. write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o ce we t address bhe , ble t hd t sd t bw t sa t ha t aw t pwe t wc t sce datai/o bhe ,ble we ce address notes 14. data i/o is high-impedance if oe or bhe and/or ble = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high?impedance state.
cy7c1041bnv33 document number: 001-06434 rev. *f page 9 of 14 figure 8. write cycle no. 3 (we controlled, oe low) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe
cy7c1041bnv33 document number: 001-06434 rev. *f page 10 of 14 ordering code definitions truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power hxxxxhigh z high z power down st andby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high z read lower bits only active (i cc ) l l h h l high z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high z write lower bits only active (i cc ) l x l h l high z data in write upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 12 CY7C1041BNV33L-12ZXC 51-85087 44-pin tsop ii (pb-free) commercial please contact local sales representative regarding availability of these parts. temperature range: c = commercial pb-free package type: z = 44-pin tsop ii speed: 12 ns l = low power voltage range: v33 = 3 v to 3.6 v bn = 0.25 m technology data width: 1 = 16-bits density: 04 = 4-mbit density family code: 1 = fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c cy 1 - 12 z 7 04 l c 1 bn v33 x
cy7c1041bnv33 document number: 001-06434 rev. *f page 11 of 14 package diagrams figure 9. 44-pin soj (400 mils) package outline, 51-85082 figure 10. 44-pin tsop ii package outline, 51-85087 51-85082 *e 51-85087 *e
cy7c1041bnv33 document number: 001-06434 rev. *f page 12 of 14 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory soj small outline j-lead ttl transistor-transistor logic tsop thin small-outline package we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? f microfarad ? s microsecond ? w microwatt ma milliampere ms millisecond mw milliwatt ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy7c1041bnv33 document number: 001-06434 rev. *f page 13 of 14 document history page document title: cy7c1041bnv33, 256 k 16 static ram document number: 001-06434 revision ecn orig. of change submission date description of change ** 423877 nxr see ecn new data sheet. *a 2899016 vkn see ecn removed industrial grade temperature related information. removed 15 ns speed bin related information. updated ordering information. updated package diagrams. *b 3109184 aju 12/13/2010 added ordering code definitions . *c 3210222 pras 03/30/2011 updated selection guide . added acronyms and units of measure . updated in new template. *d 3232637 pras 05/04/2011 fixed unit for input leakage current and output leakage current under electrical characteristics table from ma to a. *e 3403051 aju 10/12/2011 updated ordering information (removed prune part number cy7c1041bnv33l-12vxc). updated package diagrams . *f 4337921 vini 04/09/2014 updated maximum ratings : added ?static discharge voltage? and ?latch up current? details. updated package diagrams : spec 51-85082 ? changed revision from *d to *e. spec 51-85087 ? changed revision from *d to *e. updated in new template. completing sunset review.
document number: 001-06434 rev. *f revised april 9, 2014 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1041bnv33 ? cypress semiconductor corporation, 2006-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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